1. Field of the Invention
The invention pertains generally to the field of data transfer in computer systems. More particularly, it pertains to transferring information between circuits that are operated in different digital clock domains.
2. Description of the Related Art
In modern computer systems, it is often necessary to transfer data between different circuits using different clocks, often referred to as circuits in different clock domains. In at least one prior art memory system, a memory clock is used to time the transfer of data and commands to one or more memory devices over a high-speed, packet-oriented memory bus. A host clock is used to manage memory access requests received from external agents and to format the requests into appropriate command and data packets for use on the memory bus. Transferring these command and data packets from the host domain to the memory domain requires making timing adjustments.
Since the two domains may operate at significantly different clock speeds, it may take a significantly different amount of time to transfer the commands/data out of one domain than it takes to transfer the commands/data into the other domain. This can cause inefficiencies in the transfer, since the faster circuitry must wait on the slower circuitry. Various techniques can be used to minimize the loss of efficiency, such as the use of first-in first-out (FIFO) buffers between the two domains. Data can be clocked into the FIFO using one clock, and clocked out of the FIFO using the other clock.
An additional problem is created when separate blocks of data with a pre-defined timing relationship are transferred over separate channels. For example, at least one prior art memory system transfers a row command sequence over one set of memory bus lines to open a block (the row) of memory, and then transfers a column command sequence over another set of memory bus lines to select a sub-block (the column) within that open block and initiate a data transfer. Once the block is opened, several different column commands can be sequentially issued to select and transfer different sub-blocks within the open block, without the need to issue another row command. For proper operation, the column command must not be issued until a pre-defined time period after the row command has been issued, and a subsequent column command must not be issued until a different pre-defined time period after the previous column command. In a similar manner, a new row command must not be placed on the bus until another pre-defined time period after the requested data transfer from the last column command.
If these two command sequences (row and column) are transferred from the host to the memory bus through separate FIFOs, the host has no control over when each command sequence reaches the memory side of its respective FIFO, no visibility into when each command is being executed, and no visibility into when it is time to execute the next command on the memory bus. This makes it difficult to control the timing relationships from the host side. By the same token, the memory side domain has no visibility into which devices might be requesting memory access or what the order of command sequences might be until the various commands are actually received at the output of the FIFOs. This makes it difficult for the memory side to take part in any scheduling effort. This disconnect between the host and memory clock domains makes it more difficult to control the proper order of execution and the required inter-command timing delays. Using conventional approaches, providing handshaking signals between the two domains introduces excessive circuit complexity, while inserting worst-case timing delays seriously degrades performance.